The is a High Speed 4-Bit Bidirectional Universal Shift Register. As a high speed multifunctional sequential building block, it is useful in a wide variety of applications. It may be used in serial-serial, shift left, shift right, serial-parallel, parallel-serial, and parallel-parallel data register transfers. The LS194A is similar in operation to the LS195A Universal Shift Register, with added features of shift left without external connections and hold (do nothing) modes of operation. It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all Motorola TTL families.
Typical Shift Frequency of 36 MHz Asynchronous Master Reset Hold (Do Nothing) Mode Fully Synchronous Serial or Parallel Data Transfers Input Clamp Diodes Limit High Speed Termination Effects
LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L.
Mode Control Inputs Parallel Data Inputs Serial (Shift Right) Data Input Serial (Shift Left) Data Input Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Parallel Outputs (Note b)
0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L.
NOTES: a. 1 TTL Unit Load (U.L.) HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges.
FUNCTIONAL DESCRIPTION The Logic Diagram and Truth Table indicate the functional characteristics of the LS194A 4-Bit Bidirectional Shift Register. The LS194A is similar in operation to the Motorola LS195A Universal Shift Register when used in serial or parallel data register transfers. Some of the common features of the two devices are described below: All data and mode control inputs are edge-triggered, responding only to the LOW to HIGH transition of the Clock (CP). The only timing restriction, therefore, is that the mode control and selected data inputs must be stable one set-up time prior to the positive transition of the clock pulse. The register is fully synchronous, with all operations taking place in less than 15 ns (typical) making the device especially useful for implementing very high speed CPUs, or the memory buffer registers. The four parallel data inputs P2, P3) are D-type inputs. When both S0 and S1 are HIGH, the data appearing P1, P2, and P3 inputs is transferred to the Q1, Q2, and
Q3 outputs respectively following the next LOW to HIGH transition of the clock. The asynchronous Master Reset (MR), when LOW, overrides all other input conditions and forces the Q outputs LOW. Special logic features of the LS194A design which increase the range of application are described below: Two mode control inputs S 1) determine the synchronous operation of the device. As shown in the Mode Selection Table, data can be entered and shifted from left to right (shift right, Q0 Q1, etc.) or right to left (shift left, Q3 Q2, etc.), or parallel data can be entered loading all four bits of the register simultaneously. When both S0 and S1,are LOW, the existing data is retained in a "do nothing" mode without restricting the HIGH to LOW clock transition. D-type serial data inputs (DSR, DSL) are provided on both the first and last stages to allow multistage shift right or shift left data transfers without interfering with parallel load operation.
OPERATING MODE Reset Hold Shift Left Shift Right Parallel Load OUTPUTS q2 P3
L = LOW Voltage Level H = HIGH Voltage Level X = Don't Care I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to HIGH clock transition.
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current High Output Current Low Parameter Min Typ Max Unit °C mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current IIH IIL IOS ICC µA mA Min 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL 4.0 mA IOL 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
Limits Symbol fMAX tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay, Clock to Output Propagation Delay, MR to Output Min 25 Typ Max Unit MHz ns VCC 15 pF Test Conditions
1 x UNIT OF SN74LS194N